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o v e r v i e w t h e 2 4 ll c 02 s e r i a l e e p r o m has a 2,048-bit c a p a c i t y , s u p p o r t i n g t h e s t a n d a r d i 2 c ? - b u s s e rial interface. i t is fa b r i ca te d usi n g c er am at e ' s m o s t a d v anced cmos technology. it has been developed for low power and low v o l t a g e a p p l i c a t i o n s ( 1 . 8 v t o 5 . 5 v ) . o n e o f i t s m a j o r f e a t u r e i s a hardware-based write protection circuit for t h e e n t i r e m e m o r y area. hardware-based write protection is controlled by the state of the write-protect (wp) p i n . u s i n g o n e - p a g e w r i t e m o d e , you can load up to 1 6 b y t e s o f d a t a i n t o t h e e e p r o m i n a s ingle write o p e r a t i o n . a n o t h e r s i g n i f i c a n t f e a t u r e o f t h e 2 4 ll c 0 2 i s i t s s u p port for fast mode and standard mode. f e a t u r e s i 2 c - b u s i n t e r face t w o - w i r e s e r i a l i n t e r f a c e a u t o m a t i c w o r d a d d r e s s i n c r e m e n t e e p r o m 2 k - b i t ( 2 , 0 4 8 - b i t / 25 6 - by te ) s t o r a g e area 1 6 - b y t e p a ge buffer h a r d w a r e - b a s e d w r i t e p r o t e c t i o n f o r t h e e n t i r e e e p r om (using the wp pin) e e p r o m p r o g r a m m i n g voltage generated o n c h i p 1 , 000,000 erase/write c y c l e s 1 0 0 y e a r s d a t a r etention o p e r a t i ng characteristics o p e r a t i n g v o l t a g e ? 1 . 8 v t o 5 . 5 v o p e r a t i ng current ? m a x imum write current: < 3 ma at 5.5 v ? m a x i m u m read current: < 200 m a a t 5 . 5 v ? m a x i m u m s t a n d - b y c u r r e n t : < 5 m a a t 5 . 5 v o p e r a t i ng temperature range ? ? 25c to + 70c (commercial) ? ? 4 0 c to + 85c (industrial) o p e r a t ing clock frequencies ? 1 00 khz at standard mode ? 4 0 0 k h z a t f a s t m o d e e l e c t r o s t a t i c d i s c h arge (esd) ? 5 , 0 00 v (hbm) ? 5 0 0 v ( m m ) p a c k a g e s 8-pin p-dip , sop , tssop 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 1 of 19 rev 1.2 may 6,2002 * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw o r d er in g in fo rm at io n 24 llc 02 x x operating voltage type temp. grade packing llc:1.8~5.5 v ,cmos 02=2k blank: - 25 j ~+70 j blank :tube a : taping(sop8) t : taping(tssop8)
s t a r t / s t o p l o g i c s l a v e a d d r e s s c omparator w o r d address p o i n t e r r o w d e c o d e r e e p r o m c e l l array 2 5 6 x 8 b i t s h v g e n e ration t i m ing control c o n t rol logic c o l u m n d e c o d e r d a t a register d o u t a n d a c k s c l w p s d a a 0 a 1 a 2 f i g u r e 1 - 1 . 2 4 llc 02 b l o c k d i a g r a m * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 2 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
2 4 llc 02 v c c w p s c l s d a a 0 a 1 a 2 v s s n o t e : t h e 2 4 ll c0 2 i s a v ailable in 8-pin dip, sop,tssop package. f i g u r e 1 - 2 . p i n a s s i g n m e n t diagram t a b l e 1 - 1 . 2 4 ll c 02 pin descriptions n a m e t y p e d e s c r i p t i o n c i r c uit t y p e a 0 , a 1 , a 2 i nput i nput pins for device address selection. to configure a device address, t h e s e p i n s s h o u l d b e c o n n e c t e d t o t h e v c c or v s s o f t h e d e v i c e . t h e s e pins are internally pulled down to v s s . 1 v s s ? g r o u n d p i n . ? s d a i / o b i - d i r e c t i o nal data pin for the i 2 c - b us serial data interface. schmitt t r i g g e r i n put and open-drain output. an external pull-up resistor must b e c o nnected to v c c . typical values for this pull-up resistor are 4.7 k w ( 100 khz) and 1 k w (400 khz). 3 s c l i nput s c h m i t t t rigger input pin for serial clock input. 2 w p i nput i n p u t p i n f o r h a r d w a r e w r i t e p rotection control. if you tie this pin to v c c , t h e w rite function is disabled to protect previously written data in the e n t i r e m e m o r y ; i f y o u t i e i t t o v s s , t h e w r i t e f u n c t i o n i s e nabled. t his pin is internally pulled down to v s s . 1 v c c ? s i ngle power supply. ? n o t e : s e e t h e f o l l o w i n g p a ge for diagrams of pin circuit types 1, 2, and 3. * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 3 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
a 0 , a 1 , a 2 , w p f i g u r e 1-3. pin circuit type 1 s c l n o i s e f i l t er f i g u r e 1-4. pin circuit type 2 s d a v s s d a t a out n o i s e f i l t er d a t a in f i g u r e 1-5. pin circuit type 3 * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 4 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
f u n c t i o n d e s c r i p t i o n i 2 c - b u s i n t e r f a c e t h e 24 ll c 02 s u p p o r t s t h e i 2 c - b u s s e r i a l i n t e r f a c e d a ta transmission protocol. t h e two-wire bus consists of a s e r i a l d a t a line (sda) and a serial clock line (scl). the sda and the scl lines m u s t b e c o n n e c t e d t o v c c b y a p u l l - u p r esistor that is located somewhere on the bus. a n y d e v i c e t h a t p u t s d a t a o n t o t h e b u s i s d e f i n e d a s t h e ? transmitter? and any device that gets data from the bus i s t h e ? r e c e i v e r . ? t h e b u s i s c o n trolled by a master device which generates the serial clock and start/stop c o n d i t i o ns , c o n t r o lling bus access. using the a0, a1, and a2 input pins, up to eight 24 ll c0 2 d e v i c e s c a n b e c o n nected t o t h e s a m e i 2 c - b u s a s s l a ves (see figure 1-6). both the master and slaves can operate as transmitter or receiver , b u t t h e m a s t e r d e v i c e d e t e r m i n e s which bus operating mode would be active. s d a b u s m a s ter ( t r ansmitter/ r e c eiver) m c u 2 4 2 ll c t x / r x a 0 a1 a2 s l a v e 1 t o v c c or v s s t x / r x a 0 a1 a2 s l a v e 2 t o v c c or v s s t x / r x a 0 a1 a2 s l a v e 3 t o v c c or v s s t x / r x a 0 a1 a2 s l a v e 8 t o v c c or v s s v c c v c c s c l f i g u r e 1-6. typical configuration (16 kbits of memory on the i 2 c - b u s ) * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 5 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er 2 4 ll c02 2 4 ll c02 2 4 ll c02 2 4 ll c02
i 2 c - b u s p r o t o c o l s h e r e a r e s e v e r a l r u l e s f o r i 2 c - b u s t r a n s f e r s : ? a n e w d a t a t r a n s f er can be initiated only when the bus is currently not busy. ? m s b i s a l w a y s t ransferred first in transmitting data. ? d u r i n g a d a t a t r a n s f e r , t h e d a t a l i n e ( s d a ) m u s t r e m a i n s t a b l e w h e n e v e r t h e c l o c k l i n e ( s cl) is high. t h e i 2 c - b u s i n t e r f a c e s u p p o r t s t h e f o llowing communication protocols: b u s n o t b u s y : t h e s d a a n d t h e s c l l ines remain high level when the bus is not active. s t a r t condition : s t a r t c o n d i t ion is initiated by a high-to-low transition of the sda line while scl remains high l e v e l . a l l bus commands must be preceded by a start condition. s t o p c o n d ition : a s t o p c o n d i t i o n i s i n i t i a t e d b y a l o w -to-high transition of the sda line while scl remains h i g h l e v e l . a l l bus operations must be completed by a stop condition (see figure 1-7). s c l s d a s t a r t c o n d i t i o n d a t a or a c k v a l i d d a t a c h a n g e ~ ~ ~ ~ s t o p c o n d i t i o n f i g ure 1-7. data transmission sequence d a t a v a l i d : following a start condition, the data becomes valid if the data line remains stable for the duration o f t h e high period of scl. new data must be put onto the bus while scl is low. bus timing is one clock p u l s e p e r d a t a b i t . t h e n u m b e r o f d a t a b y t e s t o b e t r a n s f e r r e d i s d e t e r m i n e d b y t h e m a s t e r d e v i c e . t h e t o t a l n u m b e r o f b y t e s t h a t c a n b e t r a n s f e r red in one operation is theoretically unlimited. a c k ( a c k n o w l e d g e ) : a n a c k s i g n a l i n d i c a t e s t h a t a d a t a t r a n s f e r is completed successfully. the transmitter ( t h e m a s ter or the slave) releases the bus after transmitting eight bits. during the 9th clock, which the master g e n e r a t e s , t h e receiver pulls the sda line low to acknowledge that it successfully received the eight bits of d a t a ( s e e f i g u r e 1 - 8 ) . b u t t he slave does not send an ack if an internal write cycle is still in progress. i n d a t a r e a d o perations, the slave releases the sda line after transmitting 8 bits of data and then monitors t h e l i n e f o r a n a ck signal during the 9th clock period. if an ack is detected, the slave will continue to t r a n s m i t d a t a. if an ack is not detected, the slave terminates data transmission and waits for a stop condition t o b e i s s u e d by the master before returning to its stand-by mode. * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 6 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
m a s t e r s c l l ine d a t a from t r a n s m i t t e r a c k a c k f r o m r e c e i v e r b i t 9 b i t 1 f i g u r e 1 - 8. acknowledge response from receiver s l a v e a d d r e s s : after the master initiates a start condition, it must output the address of the device to be a c c e s s e d . t h e m o s t significant four bits of the slave address are called the ?device identifier?. the identifier f o r t h e 2 4 ll c0 2 i s ? 1 0 1 0b?. the next three bits comprise the address of a s p e c i f i c d e v i c e . t h e d e v i c e a d d r e s s i s d e f i n e d b y t he state of the a0, a1 and a2 pins. using this addressing s c h e m e , y o u c a n c a s c a d e u p t o e i g h t 24LLC02 o n the bus (see table 1-2 below). are used by the master to select which of the blocks o f i n t e r n a l m e m o r y (1 block = 2 5 6 words) are to be accessed. the bits are in effect the most significant bits o f t h e word address. r e a d / w r i t e : the final (eighth) bit of the slave address defines the type of operation to be performed. if the r / w b i t i s ? 1 ? , a r e a d o p e r a t i o n i s e x e c u t e d . i f i t i s ? 0 ? , a w r i t e o p e ration is executed. t a ble 1-2. slave device addressing d e v i c e d e vice identifier d e v i c e a d d r e s s r / w w bit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 24 llc 02 1 0 1 0 a 2 a 1 a 0 r / w n o t e : t h e b 2 , b 1 , b0 correspond to the msb of the memory array address word. * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 7 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
b y t e w r i t e o p e r a t i o n i n a c o m p l e t e byte write operation, the master transmits the slave address, word address, and one data byte to t h e 24LLC02 slave device (see figure 1-9). s l a v e a d d r e s s s t a r t w o r d address d a t a s t o p a c k a c k a c k f i g u r e 1 - 9 . b y t e w r ite operation f o l l o w i n g t h e s t a r t c o n d i t ion, the master sends the device identifier (4 bits), the device address (3 bits), and an r / w b i t s e t t o ?0? onto the bus. then the addressed 24LLC02 generates an ack a n d waits for the next byte. t h e n e x t b y t e to be transmitted by the master is the word address. this 8-bit address i s w r i t t e n i n t o t h e w o r d a d d r e s s p o i n t e r o f the 24LLC02. w h e n t h e 24LLC02 receives the word address, it responds by issuing an ack a n d then waits for the next 8-bit d a t a . w h e n it receives the data byte, the 24LLC02 a g a i n r e s p o n ds with an ack.the master terminates the t r a n s f e r b y g e n erating a stop condition, at which time the 24LLC02 begins the internal write c y c l e . w h i l e t h e i nternal write cycle is in progress, all 24LLC02 inputs are disabled and the 24LLC02 does not respond t o a d d i t i o n a l r e q u e s ts from the master. * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 8 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
p a g e w r i t e o p e r a t i o n t h e 24LLC02 can also perform 16-byte page write operation. a page write o p e r a t i o n i s i nitiated in the same w a y a s a byte write operation. however, instead of finishing the write operation a f t e r t h e f irst data byte is t r a n s f e r r e d , t h e m a s t e r c a n t r a n s m it up to 15 additional bytes. the 24 ll c02 r e s p o nds with an ack each t i m e i t r e c e i ves a complete byte of data (see figure 1-10). s l a v e a d d r e s s w o r d a d d r e s s (n) s t a r t a c k a c k d a t a ( n ) a c k a c k d a t a ( n + 1 5 ) s t o p a c k f i g u r e 1 - 1 0 . page write operation t h e 24LLC02 automatically increments the word address pointer each time it r e c e i v e s a c o m p l e t e d a ta byte. w h e n o n e b y t e h a s b e e n r e c e i v e d , the internal word address pointer increments to the next address and the n e x t d a t a b yte can be received. i f the master transmits more than 16 bytes before it generates a stop condition to end the page write operation, t h e 24LLC02 word address pointer value ?rolls over? and the previously received d a t a is overwritten.if the m a s t e r t r a n s m i t s l e s s than 16 bytes and generates a stop condition, the 24LLC02 w r i t e s t h e r e c e i v e d d a ta to t h e c o r r e s p o n d i ng eeprom address. d u r i ng a page write operation, all inputs are disabled and there is no response to additional requests from the m a s t e r u n t i l the internal write cycle is completed. * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 9 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
p o l l i n g for an ack signal w h e n t h e m a s t e r issues a stop condition to initiate a write cycle, the 24LLC02 s t a r t s an internal write cycle. t h e m a s t e r c a n t h e n immediately begin polling for an ack from the slave device. t o p o l l f o r a n a ck signal in a write operation, the master issues a start condition followed by the slave address. a s l o n g a s t h e 24LLC02 remains busy with the write operation, no ack is r e t u r ned. when the 24LLC02 c o m p l e t e s t h e write operation, it returns an ack and the master can then proceed with the next read or write o p e r a t i o n (see figure 1-11). s e n d write c o m m a n d s e nd stop condition to i nitiate write cycle s e n d s t a r t c o n d i t i o n s e n d s l ave address w i t h r / w b i t = " 0 " s t a r t n ext o p e r a t i o n a c k = " 0 " ? y es n o f i g u r e 1 - 1 1 . m a s t e r p o l l i n g f o r an ack signal from a slave device * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 10 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
h a r d w a r e - b a s e d write protection y o u c a n also write-protect the entire memory area of the 24LLC02. this method o f w r i t e protection is controlled b y t h e state of the write protect (wp) pin. w h e n t h e w p p i n i s c o n n e c t e d to v c c , a n y attempt to write a value to the memory is ignored. t h e 24LLC02 will acknowledge slave and word address, but it will not generate a n a c k n o w l e d g e a f t e r r e c e i v i n g t h e f i r s t b y te of the data. thus the write cycle will not be started when the stop c o n d i t i o n i s g e n e r a t e d . b y c o n n e c t i n g t h e w p p i n t o v s s , t h e w r i t e function is allowed for the entire memory. t h e s e w r i t e protection features effectively change the eeprom to a rom in order to prevent data from being o v e r w r i t t e n . whenever the write function is disabled, a slave address and a word address are acknowledged on t h e b u s , but data bytes are not acknowledged. c u r r e n t a ddress byte read operation t h e i n t e r n a l w o r d a d d r ess pointer maintains the address of the last word accessed, incremented by one. t h e r e f o r e , i f t he last access (either read or write) was to the address ?n?, the next read operation would access d a t a a t a d d r e s s ? n + 1 ? . w h e n t h e 24LLC02 receives a slave address with the r / w b i t s e t to ?1?, it issues a n a c k a n d s e n d s t he eight b i t s o f d a t a . t h e master does not acknowledge the transfer but it does generate a stop condition. in this way, t h e 24LLC02 effectively stops the transmission (see f igure 1-12). s l a v e a d d r e s s d a t a s t a r t a c k s t o p n o a c k f i g u r e 1-12. current address byte read operation * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 11 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
r a n d o m a d d r e s s b y t e read operation u s i n g r a n d o m r e a d o p e r a t i o n s , t h e m a s t e r c a n a c c e s s a n y memory location at any time. before it issues the s l a v e a d d r e s s w i t h the r / w bit set to ?1?, the master must first perform a ?dummy? write operation. this operation i s p e r f o r m e d i n t h e f o l l o w i n g s t e p s : 1 . t h e m a s t e r f i r s t i s s u e s a s t a r t c o ndition, the slave address, and the word address to be read. (this step sets t h e i n t e r n a l w o r d a d d r e s s p o i n t e r o f t h e 24LLC02 to the desired address.) 2 . w h e n t h e m a s t e r r e c e i v e s a n a c k f o r t h e w o r d a d d r e s s , i t immediately re-issues a start condition followed b y a n o t h e r s l a v e a d d r e s s , w i t h t he r / w b i t s e t t o ? 1 ? . 3 . t h e 24LLC02 then sends an ack and the 8-bit data stored at the desired a d d r e s s . 4 . a t t h i s p o i nt, the master does not acknowledge the transmission, but generates a stop condition instead. 5 . i n r e s p o n s e , t h e 24LLC02 stops transmitting dat a and reverts to its stand-by m o d e (see figure 1-13). s l a v e a d d r e s s w o r d address s t a r t a c k a c k s l a v e a d d r e s s a c k n o a c k s t o p s t a r t d a t a ( n ) f i g u r e 1 - 13. random address byte read operation * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:886-3-3521052 page 1 2 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
s e q u e n t i a l r e a d o p e r a t i o n s e q u e n t i a l r e a d operations can be performed in two ways: as a series of current address reads or as random a d d r e s s r eads. the first data is sent in the same way as the previous read mode used on the bus. the next time, h o w e v e r , the master responds with an ack, indicating that it requires additional data. t h e 24LLC02 continues to output data for each ack it receives. to stop the sequential read operation,the m a s t e r d o e s n o t r e s p o n d w i t h an ack, but instead issues a stop condition. u s i n g t h i s m e t h o d , d a t a i s o u tput sequentially with the data from address ?n? followed by the data from ?n+1?. the w o r d a d d r e s s p o i nter for read operations increments all word addresses, allowing the entire eeprom to be read s e q u e n t i a l l y i n a s i n g l e o p e r a t i o n . a f t e r t h e e n t i r e e e p r o m i s r e a d , the word address pointer ?rolls over? and the 24 llc 02 continues to transmit data for each ack it receives from the master ( s e e f i g u r e 1-14). s l a v e a d d r e s s d a t a ( n ) s t a r t a c k a c k n o a c k d a t a ( n + x) a c k ~ ~ f i g ure 1-14. sequential read operation * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 13 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
e l e c t r i c a l d a ta t a b l e 1-3. absolute maximum ratings ( t a = 2 5 c ) p a r a m e t e r s y m b o l c o nditions r a t i ng u n i t s u p p l y voltage v c c ? ? 0 .3 to + 7.0 v i n p u t v o ltage v i n ? ? 0 .3 to + 7.0 v o u t p u t v o l t a g e v o ? ? 0 .3 to + 7.0 v o p e r a t i n g t e m p e r a t u r e t a ? ? 4 0 t o + 8 5 c s t o r a g e temperature t s t g ? ? 6 5 t o + 1 5 0 c e l e c t r o s t a t i c d i s c h a r g e v e s d h b m 5 0 0 0 v m m 5 0 0 t a b l e 1 - 4 . d.c. electrical characteristics ( t a = ? 2 5 c t o + 7 0 c ( c ) , ? 4 0 c t o + 8 5 c ( i ) , v c c = 1 . 8 v t o 5 . 5 v ) p a r a m e t e r s y m b o l c o nditions m i n t y p m a x u n i t i n p u t low voltage v i l s cl, sda, a0, a1, a2 ? ? 0 .3 v c c v i n p u t h i g h v o l t a g e v i h 0 .7 v c c ? ? v i n p u t l e a k a g e current i l i v i n = 0 to v c c ? ? 1 0 a o u t p u t l e a k a g e c u r r e n t i l o v o = 0 to v c c ? ? 1 0 a o u t p u t l o w v o l t a g e v o l i o l = 0 . 1 5 m a , v c c = 1 . 8 v ? ? 0 . 2 v i o l = 2 . 1 m a , v c c = 2 . 5 v ? ? 0 . 4 s u p p l y c u r r e n t w r i t e i c c 1 v c c = 5.5 v, 400 khz ? ? 3 m a i c c 2 v c c = 1 .8 v, 100 khz ? ? 1 r e a d i c c 3 v c c = 5.5 v, 400 khz ? ? 0 . 2 i c c 4 v c c = 1 .8 v, 100 khz ? ? 6 0 a s t a n d - b y c u r r e n t i c c 5 v c c = s d a = s c l = 5.5 v, a ll other inputs = 0 v ? ? 5 a i c c 6 v c c = s d a = s c l = 1.8 v, a ll other inputs = 0 v ? ? 1 * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 14 of 19 rev 1. 2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
t a b l e 1-4. d.c. electrical characteristics (continued) ( t a = ? 25 c t o + 7 0 c ( c ) , ? 4 0 c t o + 8 5 c ( i ) , v c c = 1 . 8 v t o 5 . 5 v ) p a r a m e t e r s y m b o l c o nditions m i n t y p m a x u n i t i n p u t c a p a c i t ance c i n 2 5 c , 1 m h z , v c c = 5 v , v i n = 0 v , a 0, a1, a2, scl and wp pin ? ? 1 0 p f i n p u t / o u t p u t c a p a c i t a n c e c i / o 2 5 c , 1 m h z , v c c = 5 v , v i / o = 0 v , s d a p i n ? ? 1 0 t a ble 1-5. a.c. electrical characteristics ( t a = ? 25 c t o + 7 0 c ( c ) , ? 4 0 c t o + 8 5 c ( i ) , v c c = 1 . 8 v t o 5 . 5 v ) p a r a m e t e r s y m b o l c o nditions v c c = 1.8 to 5.5 v ( s t a n d a r d m o d e ) v c c = 2.5 to 5.5 v ( f a s t mode) u n i t m i n m a x m i n m a x e x t e r nal clock frequency f c l k ? 0 1 0 0 0 4 0 0 k h z c l o c k h i g h t i m e t h i g h ? 4 ? 0 . 6 ? m s c l o c k l o w t i m e t l o w ? 4 . 7 ? 1 . 3 ? r i s i n g t i m e t r s d a , s c l ? 1 ? 0 . 3 f a l l i n g t i m e t f s d a , s c l ? 0 . 3 ? 0 . 3 s t a r t condition hold time t h d:sta ? 4 ? 0 . 6 ? s t a r t condition setup time t s u : s t a ? 4 . 7 ? 0 . 6 ? d a t a input hold time t h d:dat ? 0 ? 0 ? d a t a i n p u t s e t u p t i m e t s u :dat ? 0 . 2 5 ? 0 . 1 ? s t o p c o n d ition setup time t s u:sto ? 4 ? 0 . 6 ? b u s f r e e t i m e t b u f b e f o r e n e w t r a n s m i s s i o n 4 . 7 ? 1 . 3 ? d a t a o u t p u t v alid from c l o c k l o w ( n o t e ) t a a ? 0 . 3 3 . 5 ? 0 . 9 n o i s e spike width t s p ? ? 1 0 0 ? 5 0 n s w r i t e c y c l e t i m e t w r ? ? 5 ? 5 m s n o t e s : 1 . u p o n customers request, up to 400 khz (max.) in standard mode and 1 mhz in fast mode are available. 2 . w h e n a c ting as a transmitter, the 24LLC02 must provide an internal minimum delay t i m e t o b r i d g e t h e u n d e f i n e d p e r i o d ( m i n i m u m 3 0 0 n s ) o f t h e f a l l i n g e d g e o f s c l. this is required to avoid unintended g e n e r a t i o n o f a s t a r t o r s t o p c o n d i t i o n . * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 1 5 of 19 rev 1. 2 ma y 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
s c l t l o w t f t r s d a i n t s u : s t a t h d : s t a t h d : dat t s u : d a t t s u:sto t h igh s da out t b u f t a a f i g u r e 1 - 1 5. timing diagram for bus operations 8 t h b i t w o rdn s c l s d a s t a r t c o n d i tion ~ ~ ~ ~ ~ ~ t w r s t o p c o n d i tion a c k ~ ~ f i g u r e 1 - 1 6 . w r i t e c y c l e t i m i n g d i a g ram * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 16 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er
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7 15 (4x) (4x) e1 d pin #1 indent o0.025 deep 0.006-0.008 e-pin o0.118 note 9 al a2a1 b2 b1 b e s e c eb dimensions in millimeters dimensions in inchs symbol min nom max min nom max a - - 5.33 - - 0.210 a1 0.38 - - 0.015 - - a2 3.25 3.30 3.45 0.128 0.130 0.136 b 0.36 0.46 0.56 0.014 0.018 0.02 2 b1 1.14 1.27 1.52 0.045 0.050 0.060 b2 0. 81 0.99 1.17 0.032 0.039 0.046 c 0.20 0.25 0.33 0.008 0.010 0.013 d 9.12 9.30 9.53 0.359 0.366 0.375 e 7.62 - 8.26 0.300 - 0.325 e1 6.20 6.35 6.60 0.244 0.250 0.260 e - 2.54 - - 0.100 - l 3.18 - - 0.125 - - eb 8.38 - 9.40 0.330 - 0.370 s 0.71 0.84 0.97 0.028 0.033 0.038 * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 17 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er

a 0.015x45 view "a" l h e a2 a1 b e y 7 (4x) d c 7 (4x) view "a" dimensions in millimeters dimensions in inchs symbol min nom max min nom max a 1.47 1.60 1.73 0.058 0.063 0.068 a1 0.10 - 0.25 0.004 - 0.010 a2 - 1.45 - - 0.057 - b 0.33 0.41 0.51 0.013 0.016 0.020 c 0.19 0.20 0.25 0.0075 0.008 0.0098 d 4.80 4.85 4.95 0.189 0.191 0.195 e 3.81 3.91 3.99 0.150 0.154 0.157 e - 1.27 - - 0.050 - h 5.79 5.99 6.20 0.228 0.236 0.244 l 0.38 0.71 1.27 0.015 0.028 0.050 y - - 0.10 - - 0.004 c 0 o - 8 o 0 o - 8 o * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 18 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er

a e e1 b y e c detail a detail a l 1 l e1 l1 a2 a1 d pin 1 indicator o0.70 surface polished dimensions in millimeters symbols min nom max a 1.05 1.10 1.20 a1 0.05 0.10 0.15 a2 - 1.00 1.05 b 0.20 0.25 0.28 c - 0.127 - d 2.90 3.05 3.10 e 6.20 6.40 6.60 e1 4.30 4.40 4. 50 e - 0.65 - l 0.50 0.60 0.70 l1 0.90 1.00 1.10 y - - 0.10 c 0 o 4 o 8 o * all specs and applications shown above subject to change without prior notice. 1f - 5 no.66 sec.2 nan - kan rd ., luchu , taoyuan , taiwan, r.o.c email: server@ceramate.com.tw tel:886 - 3 - 3529445 http: www.ceramate.com.tw fax:88 6 - 3 - 3521052 page 19 of 19 rev 1.2 may 6,2002 2 4 ll c0 2 2 k - bi t s er ia l ee p ro m fo r l o w p ow er

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